In https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf, Figure 10-1 and Table 10-1 describes the master AXI port, M_AXI_HPM0_FPD,  (which is used for OCPI Control Plane) as having an address of 0xA4000000 or potentially 0xA0000000 if VCU is mapped else where.

So why in runtime/hdl/include/HdlZynq.h is M_HP0_PADDR (i.e. M_AXI_HPM0_FPD from the TRM) = 0xA8000000?

If you ignore the VCU mapping, the slave address range of the HPM0 is 256MB.

Since the OpenCPI control plane requires 64MB, it is in effect aliased 4 times in that range.

So 0xa8000000 is simply the base of the upper half of the HPM0 window, and not only avoids the possible VCU window, but also avoids being adjacent to that window.

I don't know of any particular problem with using any of the 4 addresses, but using the "upper half" seemed reasonable and safe.

On 4/22/21 7:34 PM, Adam Ponchak wrote:

P {margin-top:0;margin-bottom:0;} In https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf, Figure 10-1 and Table 10-1 describes the master AXI port,  M_AXI_HPM0_FPD, (which is used for OCPI Control Plane) as having an address of 0xA4000000 or potentially 0xA0000000 if VCU is mapped else where.

So why in runtime/hdl/include/HdlZynq.h is M_HP0_PADDR (i.e.  M_AXI_HPM0_FPD from the TRM) = 0xA8000000?

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