Dominic, Specifically from line 215 to 431<https://github.com/domWalters/bsp_zcu1xx/blob/release_1.4_zynq_ultra/hdl/platforms/zcu102/fmcomms_2_3_lpc_ad9361_adc_sub_ad9361_dac_sub_LVDS.xdc> the existing zedboard fmcomms3 xdc sets a large number of input delays. The comments (.xdc lines 221 - 253) are helpful in determining what's going on. The whole idea is to: 1. pick constant values for the delay parameters (.xdc lines 259 - 267, 360 - 368), each of these 4 delays is in the range [0,15], and you might start with existing or randomly chosen values. 2. Fill the chosen constants into the commented formulas (.xdc lines 269 - 277, 370 - 378) to get the corresponding delay in nanosec. 3. Apply the calculation results as static timing constraints (.xdc lines 278 - 330, 379 - 431). 4. Build a bitstream which uses this constraint file 5. Observe timing results and verify that static timing constraints are met. 6. If timing fails, go to step 1 and repeat for different delay parameters (it's helpful to just change one value by 1 and then see if it gets better or worse, then the formulas may be useful in calculating the optimal value, a deep understanding of setup/hold and Vivado timing results is useful here). Hope that helps.