There are two areas where vendor IP is and can be used.
For "application workers", you can have alternative workers for the same
component spec that use vendor IPs.
I.e. the default is portable, and an alternative uses a coregen IP etc.
There is an example of that in
projects/tutorial/components/complex_mixer.hdl
For enabling new platforms (i.e. creating an OSP - our particular flavor
of BSP), it is common to use vendor IPs as part of adapting the platform
to the OpenCPI infrastructure.
(This process is documented in general in the OpenCPI Platform
Development Guide at opencpi.gitlab.io)
An old example of this (that is not directly usable today) is the ML605
virtex6 platform that used the PCIe core and MIG DRAM cores under ISE.
A newer example, that is a work-in-progress, is using the newer PCIe
core for the Artix7 platform from Epiq (sidekiq), that is only partially
working AFAIK.
(this is in a fork by Geon Technologies).
There is another project using a GBE core for Ethernet (for control and
RDMA/L2 data transfer), but that is currently private and not available
to look at yet. It will hopefully be posted in the gitlab repo "soon".
So the three IP types you mention are all sensibly used to adapt a
platform to OpenCPI.
And of course we instance the vendor "hard processor" IPs for things
like zynq and zynq ultrascale and stratix10 SoCs, but in those cases
there are bus-mastering hardware interfaces that we directly use for DMA.
We generally do not use any vendor soft IP.
Hope that helps...
On 4/27/20 10:47 AM, Doeve, Roy [USA] wrote:
I'm researching implementing the OpenCPI framework to integrate software and firmware into a system but one question that continues to pop up from colleagues is what if we use FPGA vendor specific IPs particularly those Hard IPs meant for the Physical Layer (ie PCIe cores, Ethernet Cores, Memory Controller IPs)? Is there a document I can reference on opencpi.org that mentions interfacing with FPGA IP Cores?
Thanks,
Roy.
There are two areas where vendor IP is and can be used.
For "application workers", you can have alternative workers for the same
component spec that use vendor IPs.
I.e. the default is portable, and an alternative uses a coregen IP etc.
There is an example of that in
projects/tutorial/components/complex_mixer.hdl
For enabling new platforms (i.e. creating an OSP - our particular flavor
of BSP), it is common to use vendor IPs as part of adapting the platform
to the OpenCPI infrastructure.
(This process is documented in general in the OpenCPI Platform
Development Guide at opencpi.gitlab.io)
An old example of this (that is not directly usable today) is the ML605
virtex6 platform that used the PCIe core and MIG DRAM cores under ISE.
A newer example, that is a work-in-progress, is using the newer PCIe
core for the Artix7 platform from Epiq (sidekiq), that is only partially
working AFAIK.
(this is in a fork by Geon Technologies).
There is another project using a GBE core for Ethernet (for control and
RDMA/L2 data transfer), but that is currently private and not available
to look at yet. It will hopefully be posted in the gitlab repo "soon".
So the three IP types you mention are all sensibly used to adapt a
platform to OpenCPI.
And of course we instance the vendor "hard processor" IPs for things
like zynq and zynq ultrascale and stratix10 SoCs, but in those cases
there are bus-mastering hardware interfaces that we directly use for DMA.
We generally do not use any vendor soft IP.
Hope that helps...
On 4/27/20 10:47 AM, Doeve, Roy [USA] wrote:
> I'm researching implementing the OpenCPI framework to integrate software and firmware into a system but one question that continues to pop up from colleagues is what if we use FPGA vendor specific IPs particularly those Hard IPs meant for the Physical Layer (ie PCIe cores, Ethernet Cores, Memory Controller IPs)? Is there a document I can reference on opencpi.org that mentions interfacing with FPGA IP Cores?
>
> Thanks,
> Roy.
>
