hdl platform port mapping
We encountered the following error regarding external signal PAD_PL_CAT_P1_D_6
We are attempting to map the signal from the AD9361_data_sub platform worker to the correct pin name in the platform XDC file.
Included below is a subset of the device worker instance. Is there an issue with how we are mapping the ports in the platform spec?
Is it necessary to specify these signals in the hdl container and/or assembly also?
Our alternative approach is to modify the XDC file to match the pin names to the AD9361 worker port names to alleviate the need for port mapping, however we need to understand how to map the ports.
=======End generated platform configuration assembly=======
For file gen/fsk_modem_asdr_cfg_1rx_1tx_m2_cnt_1rx_1tx_thruasm_asdr.xml: in HdlContainerAssembly for fsk_modem_asdr_cfg_1rx_1tx_m2_cnt_1rx_1tx_thruasm_asdr: External signal "PAD_PL_CAT_P1_D_6" specified for signal "ad9361_data_sub_P1_D_11_6(0)" of instance "pfconfig" of worker "cfg_1rx_1tx_m2" is not an external signal of the assembly
make[3]: Entering directory /home/hume-users/devinr/ocpi_projects/bsp_asdr/hdl/assemblies/fsk_modem/container-fsk_modem_asdr_cfg_1rx_1tx_m2_cnt_1rx_1tx_thruasm_asdr' /opt/opencpi/cdk/include/hdl/hdl-container.mk:112: *** Failed to process initial parameters for this worker: 1. Stop. make[3]: Leaving directory /home/hume-users/devinr/ocpi_projects/bsp_asdr/hdl/assemblies/fsk_modem/container-fsk_modem_asdr_cfg_1rx_1tx_m2_cnt_1rx_1tx_thruasm_asdr'
make[2]: *** [container-fsk_modem_asdr_cfg_1rx_1tx_m2_cnt_1rx_1tx_thruasm_asdr/target-zynq/fsk_modem_asdr_cfg_1rx_1tx_m2_cnt_1rx_1tx_thruasm_asdr.bitz] Error 2
make[2]: Leaving directory /home/hume-users/devinr/ocpi_projects/bsp_asdr/hdl/assemblies/fsk_modem' make[1]: *** [fsk_modem] Error 2 make[1]: Leaving directory /home/hume-users/devinr/ocpi_projects/bsp_asdr/hdl/assemblies'
make: *** [hdlassemblies] Error 2
In the platform spec the device worker instance port mapping is specified as:
<device worker='ad9361_data_sub'>
<Signal name='P1_D_5_0(0)' platform='PAD_PL_CAT_P1_D_0' />
<Signal name='P1_D_5_0(1)' platform='PAD_PL_CAT_P1_D_1' />
<Signal name='P1_D_5_0(2)' platform='PAD_PL_CAT_P1_D_2' />
<Signal name='P1_D_5_0(3)' platform='PAD_PL_CAT_P1_D_3' />
<Signal name='P1_D_5_0(4)' platform='PAD_PL_CAT_P1_D_4' />
<Signal name='P1_D_5_0(5)' platform='PAD_PL_CAT_P1_D_5' />
<Signal name='P1_D_11_6(0)' platform='PAD_PL_CAT_P1_D_6' />
<Signal name='P1_D_11_6(1)' platform='PAD_PL_CAT_P1_D_7' />
<Signal name='P1_D_11_6(2)' platform='PAD_PL_CAT_P1_D_8' />
<Signal name='P1_D_11_6(3)' platform='PAD_PL_CAT_P1_D_9' />
<Signal name='P1_D_11_6(4)' platform='PAD_PL_CAT_P1_D_10' />
<Signal name='P1_D_11_6(5)' platform='PAD_PL_CAT_P1_D_11' />
</device>
Devin
Devin,
Mapping a signal from the ad9361_data_sub device worker to a pin name in the XDC is certainly a valid action. To help further debug the error, can you send us the following:
- The line in your .xdc containing PAD_PL_CAT_P1_D_6
- Your assembly .xml
- Your assembly Makefile
- Your assembly container .xml
Thanks,
Brandon
From: discuss discuss-bounces@lists.opencpi.org on behalf of Devin Ridge devinr@vt.edu
Sent: Tuesday, April 30, 2019 10:27 AM
To: discuss
Subject: [Discuss OpenCPI] hdl platform port mapping
We encountered the following error regarding external signal PAD_PL_CAT_P1_D_6
We are attempting to map the signal from the AD9361_data_sub platform worker to the correct pin name in the platform XDC file.
Included below is a subset of the device worker instance. Is there an issue with how we are mapping the ports in the platform spec?
Is it necessary to specify these signals in the hdl container and/or assembly also?
Our alternative approach is to modify the XDC file to match the pin names to the AD9361 worker port names to alleviate the need for port mapping, however we need to understand how to map the ports.
=======End generated platform configuration assembly=======
For file gen/fsk_modem_asdr_cfg_1rx_1tx_m2_cnt_1rx_1tx_thruasm_asdr.xml: in HdlContainerAssembly for fsk_modem_asdr_cfg_1rx_1tx_m2_cnt_1rx_1tx_thruasm_asdr: External signal "PAD_PL_CAT_P1_D_6" specified for signal "ad9361_data_sub_P1_D_11_6(0)" of instance "pfconfig" of worker "cfg_1rx_1tx_m2" is not an external signal of the assembly
make[3]: Entering directory /home/hume-users/devinr/ocpi_projects/bsp_asdr/hdl/assemblies/fsk_modem/container-fsk_modem_asdr_cfg_1rx_1tx_m2_cnt_1rx_1tx_thruasm_asdr' /opt/opencpi/cdk/include/hdl/hdl-container.mk:112: *** Failed to process initial parameters for this worker: 1. Stop. make[3]: Leaving directory /home/hume-users/devinr/ocpi_projects/bsp_asdr/hdl/assemblies/fsk_modem/container-fsk_modem_asdr_cfg_1rx_1tx_m2_cnt_1rx_1tx_thruasm_asdr'
make[2]: *** [container-fsk_modem_asdr_cfg_1rx_1tx_m2_cnt_1rx_1tx_thruasm_asdr/target-zynq/fsk_modem_asdr_cfg_1rx_1tx_m2_cnt_1rx_1tx_thruasm_asdr.bitz] Error 2
make[2]: Leaving directory /home/hume-users/devinr/ocpi_projects/bsp_asdr/hdl/assemblies/fsk_modem' make[1]: *** [fsk_modem] Error 2 make[1]: Leaving directory /home/hume-users/devinr/ocpi_projects/bsp_asdr/hdl/assemblies'
make: *** [hdlassemblies] Error 2
In the platform spec the device worker instance port mapping is specified as:
<device worker='ad9361_data_sub'>
<Signal name='P1_D_5_0(0)' platform='PAD_PL_CAT_P1_D_0' />
<Signal name='P1_D_5_0(1)' platform='PAD_PL_CAT_P1_D_1' />
<Signal name='P1_D_5_0(2)' platform='PAD_PL_CAT_P1_D_2' />
<Signal name='P1_D_5_0(3)' platform='PAD_PL_CAT_P1_D_3' />
<Signal name='P1_D_5_0(4)' platform='PAD_PL_CAT_P1_D_4' />
<Signal name='P1_D_5_0(5)' platform='PAD_PL_CAT_P1_D_5' />
<Signal name='P1_D_11_6(0)' platform='PAD_PL_CAT_P1_D_6' />
<Signal name='P1_D_11_6(1)' platform='PAD_PL_CAT_P1_D_7' />
<Signal name='P1_D_11_6(2)' platform='PAD_PL_CAT_P1_D_8' />
<Signal name='P1_D_11_6(3)' platform='PAD_PL_CAT_P1_D_9' />
<Signal name='P1_D_11_6(4)' platform='PAD_PL_CAT_P1_D_10' />
<Signal name='P1_D_11_6(5)' platform='PAD_PL_CAT_P1_D_11' />
</device>
Devin
Brandon,
Below is the additional information:
- The line in your .xdc containing PAD_PL_CAT_P1_D_6
set_property PACKAGE_PIN AA10 [get_ports PAD_PL_CAT_P1_D_6]
- Your assembly .xml
fsk_modem.xml
<HdlAssembly> <!-- TX Chain Connections --> <Instance Worker="mfsk_mapper"> <Property Name="M_p" Value="2"/> </Instance> <Instance Worker="zero_pad"> <Property Name="DWIDTH_p" Value="16"/> </Instance> <Instance Worker="fir_real_sse" Name="tx_fir_real"> <Property Name="DATA_WIDTH_p" Value="16"/> <Property Name="COEFF_WIDTH_p" Value="16"/> <Property Name="NUM_TAPS_p" Value="64"/> </Instance> <Instance Worker="phase_to_amp_cordic"> <Property Name="DATA_WIDTH" Value="16"/> <Property Name="DATA_EXT" Value="6"/> <Property Name="STAGES" Value="16"/> </Instance> <Instance Worker="cic_int"> <Property Name="N" Value="3"/> <Property Name="M" Value="1"/> <Property Name="R" Value="16"/> <Property Name="ACC_WIDTH" Value="28"/> </Instance> <Connection Name="in_to_asm_tx_path" External="consumer"> <Port Instance="mfsk_mapper" Name="in"/> </Connection> <Connection> <Port Instance="mfsk_mapper" Name="out"/> <Port Instance="zero_pad" Name="in"/> </Connection> <Connection> <Port Instance="zero_pad" Name="out"/> <Port Instance="tx_fir_real" Name="in"/> </Connection> <Connection> <Port Instance="tx_fir_real" Name="out"/> <Port Instance="phase_to_amp_cordic" Name="in"/> </Connection> <Connection> <Port Instance="phase_to_amp_cordic" Name="out"/> <Port Instance="cic_int" Name="in"/> </Connection> <Connection Name="out_from_asm_tx_path_to_dac" External="producer"> <Port Instance="cic_int" Name="out"/> </Connection> <!-- RX Chain Connections --> <Instance Worker="dc_offset_filter"> <Property Name="PEAK_MONITOR_p" Value="true"/> </Instance> <Instance Worker="iq_imbalance_fixer"> <Property Name="PEAK_MONITOR_p" Value="true"/> </Instance> <Instance Worker="complex_mixer"> <Property Name="NCO_DATA_WIDTH_p" Value="12"/> <Property Name="INPUT_DATA_WIDTH_p" Value="12"/> <Property Name="PEAK_MONITOR_p" Value="true"/> </Instance> <Instance Worker="cic_dec"> <Property Name="N" Value="3"/> <Property Name="M" Value="1"/> <Property Name="R" Value="16"/> <Property Name="ACC_WIDTH" Value="28"/> </Instance> <Instance Worker="rp_cordic"> <Property Name="DATA_WIDTH" Value="16"/> <Property Name="DATA_EXT" Value="6"/> <Property Name="STAGES" Value="16"/> </Instance> <Instance Worker="fir_real_sse" Name="rx_fir_real"> <Property Name="DATA_WIDTH_p" Value="16"/> <Property Name="COEFF_WIDTH_p" Value="16"/> <Property Name="NUM_TAPS_p" Value="64"/> </Instance> <Connection Name="in_to_asm_rx_path_from_adc" External="consumer"> <Port Instance="dc_offset_filter" Name="in"/> </Connection> <Connection> <Port Instance="dc_offset_filter" Name="out"/> <Port Instance="iq_imbalance_fixer" Name="in"/> </Connection> <Connection> <Port Instance="iq_imbalance_fixer" Name="out"/> <Port Instance="complex_mixer" Name="in"/> </Connection> <Connection> <Port Instance="complex_mixer" Name="out"/> <Port Instance="cic_dec" Name="in"/> </Connection> <Connection> <Port Instance="cic_dec" Name="out"/> <Port Instance="rp_cordic" Name="in"/> </Connection> <Connection> <Port Instance="rp_cordic" Name="out"/> <Port Instance="rx_fir_real" Name="in"/> </Connection> <Connection Name="out_from_asm_rx_path" External="producer"> <Port Instance="rx_fir_real" Name="out"/> </Connection> </HdlAssembly>- Your assembly Makefile
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distributed with this source distribution.
This file is part of OpenCPI http://www.opencpi.org
OpenCPI is free software: you can redistribute it and/or modify it under the
terms of the GNU Lesser General Public License as published by the Free
Software Foundation, either version 3 of the License, or (at your option) any
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OpenCPI is distributed in the hope that it will be useful, but WITHOUT ANY
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A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
details.
You should have received a copy of the GNU Lesser General Public License along
with this program. If not, see http://www.gnu.org/licenses/.
$(if $(realpath $(OCPI_CDK_DIR)),,$(error The OCPI_CDK_DIR environment variable is not set correctly.))
Containers= \
cnt_1rx_1tx_thruasm_asdr
export VivadoExtraOptions_route:= -directive NoTimingRelaxation
DefaultContainers=
ExcludePlatforms=isim modelsim xsim
Libraries+=misc_prims util_prims dsp_prims comms_prims
include $(OCPI_CDK_DIR)/include/hdl/hdl-assembly.mk
- Your assembly container .xml
cnt_1rx_1tx_thruasm_asdr.xml
<!-- filename: cnt_1rx_1tx_thruasm_asdr.xml --> <!-- filename description: cnt (this is a container) --> <!-- 1rx (number of RX channels used) --> <!-- 1tx (number of TX channels used) --> <!-- thruasm (container architecture description) --> <!-- asdr (frontend and/or slot descriptions, if applicable) --> <!-- (other details, if applicable) --> <!-- asdr (platform description, if applicable) --> <!-- .xml --> <!-- CPU FPGA --> <!-- ______ _________________________________________ --> <!-- + + + + --> <!-- | | i | container ___ | --> <!-- | | n | + + | --> <!-- | |*t*|*********************************|dev| | --> <!-- | | e | (3) * +___+ | --> <!-- | | r | * | --> <!-- | | c | ______________ * | --> <!-- | | o | + assembly + *(1) | --> <!-- | | n | | | * | --> <!-- | | n | (2) | | * | --> <!-- | |*e*|*********| |**** | --> <!-- | | c | | | | --> <!-- | | t | | | | --> <!-- +______+ +_________+_____________+_________________+ --> <!-- --> <HdlContainer Config="cfg_1rx_1tx_m2" Platform="asdr"> <!-- (1) external-to-FPGA device (worker) to FPGA assembly connections --> <!--Connection External="<assembly_port_name>" Port="<device_port_name>" Device="<device_name>" Card="<card_name>" (required if card is used) Slot="<slot_name>" (required if more than one platform slot of the card slot type exists) --> <!-- e.g. <Connection External="in_to_asm_rx_path_from_adc" Port="out" Device="lime_adc"/> --> <!-- e.g. <Connection External="out_from_asm_tx_path_to_dac" Port="in" Device="lime_dac"/> --> <Connection External="in_to_asm_rx_path_from_adc" Port="out" Device="ad9361_adc0"/> <Connection External="out_from_asm_tx_path_to_dac" Port="in" Device="ad9361_dac0" /> <!-- (2) FPGA assembly to CPU interconnect connections --> <!--Connection External="<assembly_port_name>" Interconnect="<interconnect_name, probably zynq or pcie>"/--> <!-- e.g. <Connection External="out_from_asm_rx_path" Interconnect="zynq"/> --> <!-- e.g. <Connection External="in_to_asm_tx_path" Interconnect="zynq"/> --> <Connection External="out_from_asm_rx_path" Interconnect="zynq"/> <Connection External="in_to_asm_tx_path" Interconnect="zynq"/> <!-- (3) external-to-FPGA device (worker) to CPU interconnect connections (bypassing the assembly)--> <!--Connection Device="<device_name>" Port="<device_port_name>" Card="<card_name>" (required if card is used) Slot="<slot_name>" (required if more than one platform slot of the card slot type exists) Interconnect="<interconnect_name, probably zynq or pcie>"/--> <!-- e.g. <Connection Device="lime_adc" Port="out" Interconnect="pcie"/> --> <!-- e.g. <Connection Device="lime_dac" Port="in" Interconnect="pcie"/> --> </HdlContainer>From: "Brandon Luquette" bluquette@geontech.onmicrosoft.com
To: "Devin Ridge" devinr@vt.edu, "discuss" discuss@lists.opencpi.org
Sent: Tuesday, April 30, 2019 11:34:05 AM
Subject: Re: hdl platform port mapping
Devin,
Mapping a signal from the ad9361_data_sub device worker to a pin name in the XDC is certainly a valid action. To help further debug the error, can you send us the following:
1. The line in your .xdc containing PAD_PL_CAT_P1_D_6
2. Your assembly .xml
3. Your assembly Makefile
4. Your assembly container .xml
Thanks,
Brandon
From: discuss discuss-bounces@lists.opencpi.org on behalf of Devin Ridge devinr@vt.edu
Sent: Tuesday, April 30, 2019 10:27 AM
To: discuss
Subject: [Discuss OpenCPI] hdl platform port mapping
We encountered the following error regarding external signal PAD_PL_CAT_P1_D_6
We are attempting to map the signal from the AD9361_data_sub platform worker to the correct pin name in the platform XDC file.
Included below is a subset of the device worker instance. Is there an issue with how we are mapping the ports in the platform spec?
Is it necessary to specify these signals in the hdl container and/or assembly also?
Our alternative approach is to modify the XDC file to match the pin names to the AD9361 worker port names to alleviate the need for port mapping, however we need to understand how to map the ports.
=======End generated platform configuration assembly=======
For file gen/fsk_modem_asdr_cfg_1rx_1tx_m2_cnt_1rx_1tx_thruasm_asdr.xml: in HdlContainerAssembly for fsk_modem_asdr_cfg_1rx_1tx_m2_cnt_1rx_1tx_thruasm_asdr: External signal "PAD_PL_CAT_P1_D_6" specified for signal "ad9361_data_sub_P1_D_11_6(0)" of instance "pfconfig" of worker "cfg_1rx_1tx_m2" is not an external signal of the assembly
make[3]: Entering directory /home/hume-users/devinr/ocpi_projects/bsp_asdr/hdl/assemblies/fsk_modem/container-fsk_modem_asdr_cfg_1rx_1tx_m2_cnt_1rx_1tx_thruasm_asdr' /opt/opencpi/cdk/include/hdl/hdl-container.mk:112: *** Failed to process initial parameters for this worker: 1. Stop. make[3]: Leaving directory /home/hume-users/devinr/ocpi_projects/bsp_asdr/hdl/assemblies/fsk_modem/container-fsk_modem_asdr_cfg_1rx_1tx_m2_cnt_1rx_1tx_thruasm_asdr'
make[2]: *** [container-fsk_modem_asdr_cfg_1rx_1tx_m2_cnt_1rx_1tx_thruasm_asdr/target-zynq/fsk_modem_asdr_cfg_1rx_1tx_m2_cnt_1rx_1tx_thruasm_asdr.bitz] Error 2
make[2]: Leaving directory /home/hume-users/devinr/ocpi_projects/bsp_asdr/hdl/assemblies/fsk_modem' make[1]: *** [fsk_modem] Error 2 make[1]: Leaving directory /home/hume-users/devinr/ocpi_projects/bsp_asdr/hdl/assemblies'
make: *** [hdlassemblies] Error 2
In the platform spec the device worker instance port mapping is specified as:
<device worker='ad9361_data_sub'>
<Signal name='P1_D_5_0(0)' platform='PAD_PL_CAT_P1_D_0' />
<Signal name='P1_D_5_0(1)' platform='PAD_PL_CAT_P1_D_1' />
<Signal name='P1_D_5_0(2)' platform='PAD_PL_CAT_P1_D_2' />
<Signal name='P1_D_5_0(3)' platform='PAD_PL_CAT_P1_D_3' />
<Signal name='P1_D_5_0(4)' platform='PAD_PL_CAT_P1_D_4' />
<Signal name='P1_D_5_0(5)' platform='PAD_PL_CAT_P1_D_5' />
<Signal name='P1_D_11_6(0)' platform='PAD_PL_CAT_P1_D_6' />
<Signal name='P1_D_11_6(1)' platform='PAD_PL_CAT_P1_D_7' />
<Signal name='P1_D_11_6(2)' platform='PAD_PL_CAT_P1_D_8' />
<Signal name='P1_D_11_6(3)' platform='PAD_PL_CAT_P1_D_9' />
<Signal name='P1_D_11_6(4)' platform='PAD_PL_CAT_P1_D_10' />
<Signal name='P1_D_11_6(5)' platform='PAD_PL_CAT_P1_D_11' />
</device>
Devin
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Hi Devin,
I have been able to replicate your issue locally, and it appears the ability to change a signal name to match a different name in the XDC is currently not supported, specifically for device workers not using the slots/cards paradigm (like e3xx).
The quickest workaround would be to modify the XDC file as you mentioned. The naming convention which should be used is:
<device worker name>_<signal name>
For the example you gave, you will need to change 2 things:
First, you'll have to changing the XDC lines from:
set_property PACKAGE_PIN AA10 [get_ports PAD_PL_CAT_P1_D_6]
To:
set_property PACKAGE_PIN AA10 [get_ports {ad9361_data_sub_P1_D_11_6[0]}]
Second, you'll have to modify your platform XML from:
<device worker='ad9361_data_sub'> <Signal name='P1_D_5_0(0)' platform='PAD_PL_CAT_P1_D_0' /> <Signal name='P1_D_5_0(1)' platform='PAD_PL_CAT_P1_D_1' /> <Signal name='P1_D_5_0(2)' platform='PAD_PL_CAT_P1_D_2' /> <Signal name='P1_D_5_0(3)' platform='PAD_PL_CAT_P1_D_3' /> <Signal name='P1_D_5_0(4)' platform='PAD_PL_CAT_P1_D_4' /> <Signal name='P1_D_5_0(5)' platform='PAD_PL_CAT_P1_D_5' /> <Signal name='P1_D_11_6(0)' platform='PAD_PL_CAT_P1_D_6' /> <Signal name='P1_D_11_6(1)' platform='PAD_PL_CAT_P1_D_7' /> <Signal name='P1_D_11_6(2)' platform='PAD_PL_CAT_P1_D_8' /> <Signal name='P1_D_11_6(3)' platform='PAD_PL_CAT_P1_D_9' /> <Signal name='P1_D_11_6(4)' platform='PAD_PL_CAT_P1_D_10' /> <Signal name='P1_D_11_6(5)' platform='PAD_PL_CAT_P1_D_11' /> </device>to:
<device worker='ad9361_data_sub'/>These two changes should resolve your issue. Please let us know if does not resolve the problem.
Brandon
From: Devin Ridge devinr@vt.edu
Sent: Tuesday, April 30, 2019 11:51 AM
To: Brandon Luquette; discuss
Subject: Re: hdl platform port mapping
Brandon,
Below is the additional information:
- The line in your .xdc containing PAD_PL_CAT_P1_D_6
set_property PACKAGE_PIN AA10 [get_ports PAD_PL_CAT_P1_D_6]
- Your assembly .xml
fsk_modem.xml
<HdlAssembly> <!-- TX Chain Connections --> <Instance Worker="mfsk_mapper"> <Property Name="M_p" Value="2"/> </Instance> <Instance Worker="zero_pad"> <Property Name="DWIDTH_p" Value="16"/> </Instance> <Instance Worker="fir_real_sse" Name="tx_fir_real"> <Property Name="DATA_WIDTH_p" Value="16"/> <Property Name="COEFF_WIDTH_p" Value="16"/> <Property Name="NUM_TAPS_p" Value="64"/> </Instance> <Instance Worker="phase_to_amp_cordic"> <Property Name="DATA_WIDTH" Value="16"/> <Property Name="DATA_EXT" Value="6"/> <Property Name="STAGES" Value="16"/> </Instance> <Instance Worker="cic_int"> <Property Name="N" Value="3"/> <Property Name="M" Value="1"/> <Property Name="R" Value="16"/> <Property Name="ACC_WIDTH" Value="28"/> </Instance> <Connection Name="in_to_asm_tx_path" External="consumer"> <Port Instance="mfsk_mapper" Name="in"/> </Connection> <Connection> <Port Instance="mfsk_mapper" Name="out"/> <Port Instance="zero_pad" Name="in"/> </Connection> <Connection> <Port Instance="zero_pad" Name="out"/> <Port Instance="tx_fir_real" Name="in"/> </Connection> <Connection> <Port Instance="tx_fir_real" Name="out"/> <Port Instance="phase_to_amp_cordic" Name="in"/> </Connection> <Connection> <Port Instance="phase_to_amp_cordic" Name="out"/> <Port Instance="cic_int" Name="in"/> </Connection> <Connection Name="out_from_asm_tx_path_to_dac" External="producer"> <Port Instance="cic_int" Name="out"/> </Connection> <!-- RX Chain Connections --> <Instance Worker="dc_offset_filter"> <Property Name="PEAK_MONITOR_p" Value="true"/> </Instance> <Instance Worker="iq_imbalance_fixer"> <Property Name="PEAK_MONITOR_p" Value="true"/> </Instance> <Instance Worker="complex_mixer"> <Property Name="NCO_DATA_WIDTH_p" Value="12"/> <Property Name="INPUT_DATA_WIDTH_p" Value="12"/> <Property Name="PEAK_MONITOR_p" Value="true"/> </Instance> <Instance Worker="cic_dec"> <Property Name="N" Value="3"/> <Property Name="M" Value="1"/> <Property Name="R" Value="16"/> <Property Name="ACC_WIDTH" Value="28"/> </Instance> <Instance Worker="rp_cordic"> <Property Name="DATA_WIDTH" Value="16"/> <Property Name="DATA_EXT" Value="6"/> <Property Name="STAGES" Value="16"/> </Instance> <Instance Worker="fir_real_sse" Name="rx_fir_real"> <Property Name="DATA_WIDTH_p" Value="16"/> <Property Name="COEFF_WIDTH_p" Value="16"/> <Property Name="NUM_TAPS_p" Value="64"/> </Instance> <Connection Name="in_to_asm_rx_path_from_adc" External="consumer"> <Port Instance="dc_offset_filter" Name="in"/> </Connection> <Connection> <Port Instance="dc_offset_filter" Name="out"/> <Port Instance="iq_imbalance_fixer" Name="in"/> </Connection> <Connection> <Port Instance="iq_imbalance_fixer" Name="out"/> <Port Instance="complex_mixer" Name="in"/> </Connection> <Connection> <Port Instance="complex_mixer" Name="out"/> <Port Instance="cic_dec" Name="in"/> </Connection> <Connection> <Port Instance="cic_dec" Name="out"/> <Port Instance="rp_cordic" Name="in"/> </Connection> <Connection> <Port Instance="rp_cordic" Name="out"/> <Port Instance="rx_fir_real" Name="in"/> </Connection> <Connection Name="out_from_asm_rx_path" External="producer"> <Port Instance="rx_fir_real" Name="out"/> </Connection> </HdlAssembly>- Your assembly Makefile
This file is protected by Copyright. Please refer to the COPYRIGHT file
distributed with this source distribution.
This file is part of OpenCPI http://www.opencpi.org
OpenCPI is free software: you can redistribute it and/or modify it under the
terms of the GNU Lesser General Public License as published by the Free
Software Foundation, either version 3 of the License, or (at your option) any
later version.
OpenCPI is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
details.
You should have received a copy of the GNU Lesser General Public License along
with this program. If not, see http://www.gnu.org/licenses/.
$(if $(realpath $(OCPI_CDK_DIR)),,$(error The OCPI_CDK_DIR environment variable is not set correctly.))
Containers=
cnt_1rx_1tx_thruasm_asdr
export VivadoExtraOptions_route:= -directive NoTimingRelaxation
DefaultContainers=
ExcludePlatforms=isim modelsim xsim
Libraries+=misc_prims util_prims dsp_prims comms_prims
include $(OCPI_CDK_DIR)/include/hdl/hdl-assembly.mk
- Your assembly container .xml
cnt_1rx_1tx_thruasm_asdr.xml
<!-- filename: cnt_1rx_1tx_thruasm_asdr.xml --> <!-- filename description: cnt (this is a container) --> <!-- 1rx (number of RX channels used) --> <!-- 1tx (number of TX channels used) --> <!-- thruasm (container architecture description) --> <!-- asdr (frontend and/or slot descriptions, if applicable) --> <!-- (other details, if applicable) --> <!-- asdr (platform description, if applicable) --> <!-- .xml --> <!-- CPU FPGA --> <!-- ______ _________________________________________ --> <!-- + + + + --> <!-- | | i | container ___ | --> <!-- | | n | + + | --> <!-- | |*t*|*********************************|dev| | --> <!-- | | e | (3) * +___+ | --> <!-- | | r | * | --> <!-- | | c | ______________ * | --> <!-- | | o | + assembly + *(1) | --> <!-- | | n | | | * | --> <!-- | | n | (2) | | * | --> <!-- | |*e*|*********| |**** | --> <!-- | | c | | | | --> <!-- | | t | | | | --> <!-- +______+ +_________+_____________+_________________+ --> <!-- --> <HdlContainer Config="cfg_1rx_1tx_m2" Platform="asdr"> <!-- (1) external-to-FPGA device (worker) to FPGA assembly connections --> <!--Connection External="<assembly_port_name>" Port="<device_port_name>" Device="<device_name>" Card="<card_name>" (required if card is used) Slot="<slot_name>" (required if more than one platform slot of the card slot type exists) --> <!-- e.g. <Connection External="in_to_asm_rx_path_from_adc" Port="out" Device="lime_adc"/> --> <!-- e.g. <Connection External="out_from_asm_tx_path_to_dac" Port="in" Device="lime_dac"/> --> <Connection External="in_to_asm_rx_path_from_adc" Port="out" Device="ad9361_adc0"/> <Connection External="out_from_asm_tx_path_to_dac" Port="in" Device="ad9361_dac0" /> <!-- (2) FPGA assembly to CPU interconnect connections --> <!--Connection External="<assembly_port_name>" Interconnect="<interconnect_name, probably zynq or pcie>"/--> <!-- e.g. <Connection External="out_from_asm_rx_path" Interconnect="zynq"/> --> <!-- e.g. <Connection External="in_to_asm_tx_path" Interconnect="zynq"/> --> <Connection External="out_from_asm_rx_path" Interconnect="zynq"/> <Connection External="in_to_asm_tx_path" Interconnect="zynq"/> <!-- (3) external-to-FPGA device (worker) to CPU interconnect connections (bypassing the assembly)--> <!--Connection Device="<device_name>" Port="<device_port_name>" Card="<card_name>" (required if card is used) Slot="<slot_name>" (required if more than one platform slot of the card slot type exists) Interconnect="<interconnect_name, probably zynq or pcie>"/--> <!-- e.g. <Connection Device="lime_adc" Port="out" Interconnect="pcie"/> --> <!-- e.g. <Connection Device="lime_dac" Port="in" Interconnect="pcie"/> --> </HdlContainer>From: "Brandon Luquette" bluquette@geontech.onmicrosoft.com
To: "Devin Ridge" devinr@vt.edu, "discuss" discuss@lists.opencpi.org
Sent: Tuesday, April 30, 2019 11:34:05 AM
Subject: Re: hdl platform port mapping
Devin,
Mapping a signal from the ad9361_data_sub device worker to a pin name in the XDC is certainly a valid action. To help further debug the error, can you send us the following:
- The line in your .xdc containing PAD_PL_CAT_P1_D_6
- Your assembly .xml
- Your assembly Makefile
- Your assembly container .xml
Thanks,
Brandon
From: discuss discuss-bounces@lists.opencpi.org on behalf of Devin Ridge devinr@vt.edu
Sent: Tuesday, April 30, 2019 10:27 AM
To: discuss
Subject: [Discuss OpenCPI] hdl platform port mapping
We encountered the following error regarding external signal PAD_PL_CAT_P1_D_6
We are attempting to map the signal from the AD9361_data_sub platform worker to the correct pin name in the platform XDC file.
Included below is a subset of the device worker instance. Is there an issue with how we are mapping the ports in the platform spec?
Is it necessary to specify these signals in the hdl container and/or assembly also?
Our alternative approach is to modify the XDC file to match the pin names to the AD9361 worker port names to alleviate the need for port mapping, however we need to understand how to map the ports.
=======End generated platform configuration assembly=======
For file gen/fsk_modem_asdr_cfg_1rx_1tx_m2_cnt_1rx_1tx_thruasm_asdr.xml: in HdlContainerAssembly for fsk_modem_asdr_cfg_1rx_1tx_m2_cnt_1rx_1tx_thruasm_asdr: External signal "PAD_PL_CAT_P1_D_6" specified for signal "ad9361_data_sub_P1_D_11_6(0)" of instance "pfconfig" of worker "cfg_1rx_1tx_m2" is not an external signal of the assembly
make[3]: Entering directory /home/hume-users/devinr/ocpi_projects/bsp_asdr/hdl/assemblies/fsk_modem/container-fsk_modem_asdr_cfg_1rx_1tx_m2_cnt_1rx_1tx_thruasm_asdr' /opt/opencpi/cdk/include/hdl/hdl-container.mk:112: *** Failed to process initial parameters for this worker: 1. Stop. make[3]: Leaving directory /home/hume-users/devinr/ocpi_projects/bsp_asdr/hdl/assemblies/fsk_modem/container-fsk_modem_asdr_cfg_1rx_1tx_m2_cnt_1rx_1tx_thruasm_asdr'
make[2]: *** [container-fsk_modem_asdr_cfg_1rx_1tx_m2_cnt_1rx_1tx_thruasm_asdr/target-zynq/fsk_modem_asdr_cfg_1rx_1tx_m2_cnt_1rx_1tx_thruasm_asdr.bitz] Error 2
make[2]: Leaving directory /home/hume-users/devinr/ocpi_projects/bsp_asdr/hdl/assemblies/fsk_modem' make[1]: *** [fsk_modem] Error 2 make[1]: Leaving directory /home/hume-users/devinr/ocpi_projects/bsp_asdr/hdl/assemblies'
make: *** [hdlassemblies] Error 2
In the platform spec the device worker instance port mapping is specified as:
<device worker='ad9361_data_sub'>
<Signal name='P1_D_5_0(0)' platform='PAD_PL_CAT_P1_D_0' />
<Signal name='P1_D_5_0(1)' platform='PAD_PL_CAT_P1_D_1' />
<Signal name='P1_D_5_0(2)' platform='PAD_PL_CAT_P1_D_2' />
<Signal name='P1_D_5_0(3)' platform='PAD_PL_CAT_P1_D_3' />
<Signal name='P1_D_5_0(4)' platform='PAD_PL_CAT_P1_D_4' />
<Signal name='P1_D_5_0(5)' platform='PAD_PL_CAT_P1_D_5' />
<Signal name='P1_D_11_6(0)' platform='PAD_PL_CAT_P1_D_6' />
<Signal name='P1_D_11_6(1)' platform='PAD_PL_CAT_P1_D_7' />
<Signal name='P1_D_11_6(2)' platform='PAD_PL_CAT_P1_D_8' />
<Signal name='P1_D_11_6(3)' platform='PAD_PL_CAT_P1_D_9' />
<Signal name='P1_D_11_6(4)' platform='PAD_PL_CAT_P1_D_10' />
<Signal name='P1_D_11_6(5)' platform='PAD_PL_CAT_P1_D_11' />
</device>
Devin
Hello again,
After further investigation, there appears to be an alternative to modifying the XDC file to match the signal names. What was missing from your original email was signal declarations to the HdlPlatform describing the pins described in the XDC.
The HdlPlatform XML would contain the device instance:
<device worker='ad9361_data_sub'> <Signal name='P1_D_5_0(0)' platform='PAD_PL_CAT_P1_D_0' /> <Signal name='P1_D_5_0(1)' platform='PAD_PL_CAT_P1_D_1' /> <Signal name='P1_D_5_0(2)' platform='PAD_PL_CAT_P1_D_2' /> <Signal name='P1_D_5_0(3)' platform='PAD_PL_CAT_P1_D_3' /> <Signal name='P1_D_5_0(4)' platform='PAD_PL_CAT_P1_D_4' /> <Signal name='P1_D_5_0(5)' platform='PAD_PL_CAT_P1_D_5' /> <Signal name='P1_D_11_6(0)' platform='PAD_PL_CAT_P1_D_6' /> <Signal name='P1_D_11_6(1)' platform='PAD_PL_CAT_P1_D_7' /> <Signal name='P1_D_11_6(2)' platform='PAD_PL_CAT_P1_D_8' /> <Signal name='P1_D_11_6(3)' platform='PAD_PL_CAT_P1_D_9' /> <Signal name='P1_D_11_6(4)' platform='PAD_PL_CAT_P1_D_10' /> <Signal name='P1_D_11_6(5)' platform='PAD_PL_CAT_P1_D_11' /> </device>and signal declarations for any signals which required mapping:
<signal <direction>="PAD_PL_CAT_P1_D_0"/>
<signal <direction>="PAD_PL_CAT_P1_D_1"/>
...
You should be able to derive the direction of the signal from the configuration of the ad9361_data_sub you are using. Both this approach and the approach mentioned yesterday (modifying the XDC file) should work.
Thanks,
Brandon
From: discuss discuss-bounces@lists.opencpi.org on behalf of Brandon Luquette bluquette@geontech.onmicrosoft.com
Sent: Monday, May 6, 2019 2:43 PM
To: Devin Ridge; discuss
Subject: Re: [Discuss OpenCPI] hdl platform port mapping
Hi Devin,
I have been able to replicate your issue locally, and it appears the ability to change a signal name to match a different name in the XDC is currently not supported, specifically for device workers not using the slots/cards paradigm (like e3xx).
The quickest workaround would be to modify the XDC file as you mentioned. The naming convention which should be used is:
<device worker name>_<signal name>
For the example you gave, you will need to change 2 things:
First, you'll have to changing the XDC lines from:
set_property PACKAGE_PIN AA10 [get_ports PAD_PL_CAT_P1_D_6]
To:
set_property PACKAGE_PIN AA10 [get_ports {ad9361_data_sub_P1_D_11_6[0]}]
Second, you'll have to modify your platform XML from:
<device worker='ad9361_data_sub'> <Signal name='P1_D_5_0(0)' platform='PAD_PL_CAT_P1_D_0' /> <Signal name='P1_D_5_0(1)' platform='PAD_PL_CAT_P1_D_1' /> <Signal name='P1_D_5_0(2)' platform='PAD_PL_CAT_P1_D_2' /> <Signal name='P1_D_5_0(3)' platform='PAD_PL_CAT_P1_D_3' /> <Signal name='P1_D_5_0(4)' platform='PAD_PL_CAT_P1_D_4' /> <Signal name='P1_D_5_0(5)' platform='PAD_PL_CAT_P1_D_5' /> <Signal name='P1_D_11_6(0)' platform='PAD_PL_CAT_P1_D_6' /> <Signal name='P1_D_11_6(1)' platform='PAD_PL_CAT_P1_D_7' /> <Signal name='P1_D_11_6(2)' platform='PAD_PL_CAT_P1_D_8' /> <Signal name='P1_D_11_6(3)' platform='PAD_PL_CAT_P1_D_9' /> <Signal name='P1_D_11_6(4)' platform='PAD_PL_CAT_P1_D_10' /> <Signal name='P1_D_11_6(5)' platform='PAD_PL_CAT_P1_D_11' /> </device>to:
<device worker='ad9361_data_sub'/>These two changes should resolve your issue. Please let us know if does not resolve the problem.
Brandon
From: Devin Ridge devinr@vt.edu
Sent: Tuesday, April 30, 2019 11:51 AM
To: Brandon Luquette; discuss
Subject: Re: hdl platform port mapping
Brandon,
Below is the additional information:
- The line in your .xdc containing PAD_PL_CAT_P1_D_6
set_property PACKAGE_PIN AA10 [get_ports PAD_PL_CAT_P1_D_6]
- Your assembly .xml
fsk_modem.xml
<HdlAssembly> <!-- TX Chain Connections --> <Instance Worker="mfsk_mapper"> <Property Name="M_p" Value="2"/> </Instance> <Instance Worker="zero_pad"> <Property Name="DWIDTH_p" Value="16"/> </Instance> <Instance Worker="fir_real_sse" Name="tx_fir_real"> <Property Name="DATA_WIDTH_p" Value="16"/> <Property Name="COEFF_WIDTH_p" Value="16"/> <Property Name="NUM_TAPS_p" Value="64"/> </Instance> <Instance Worker="phase_to_amp_cordic"> <Property Name="DATA_WIDTH" Value="16"/> <Property Name="DATA_EXT" Value="6"/> <Property Name="STAGES" Value="16"/> </Instance> <Instance Worker="cic_int"> <Property Name="N" Value="3"/> <Property Name="M" Value="1"/> <Property Name="R" Value="16"/> <Property Name="ACC_WIDTH" Value="28"/> </Instance> <Connection Name="in_to_asm_tx_path" External="consumer"> <Port Instance="mfsk_mapper" Name="in"/> </Connection> <Connection> <Port Instance="mfsk_mapper" Name="out"/> <Port Instance="zero_pad" Name="in"/> </Connection> <Connection> <Port Instance="zero_pad" Name="out"/> <Port Instance="tx_fir_real" Name="in"/> </Connection> <Connection> <Port Instance="tx_fir_real" Name="out"/> <Port Instance="phase_to_amp_cordic" Name="in"/> </Connection> <Connection> <Port Instance="phase_to_amp_cordic" Name="out"/> <Port Instance="cic_int" Name="in"/> </Connection> <Connection Name="out_from_asm_tx_path_to_dac" External="producer"> <Port Instance="cic_int" Name="out"/> </Connection> <!-- RX Chain Connections --> <Instance Worker="dc_offset_filter"> <Property Name="PEAK_MONITOR_p" Value="true"/> </Instance> <Instance Worker="iq_imbalance_fixer"> <Property Name="PEAK_MONITOR_p" Value="true"/> </Instance> <Instance Worker="complex_mixer"> <Property Name="NCO_DATA_WIDTH_p" Value="12"/> <Property Name="INPUT_DATA_WIDTH_p" Value="12"/> <Property Name="PEAK_MONITOR_p" Value="true"/> </Instance> <Instance Worker="cic_dec"> <Property Name="N" Value="3"/> <Property Name="M" Value="1"/> <Property Name="R" Value="16"/> <Property Name="ACC_WIDTH" Value="28"/> </Instance> <Instance Worker="rp_cordic"> <Property Name="DATA_WIDTH" Value="16"/> <Property Name="DATA_EXT" Value="6"/> <Property Name="STAGES" Value="16"/> </Instance> <Instance Worker="fir_real_sse" Name="rx_fir_real"> <Property Name="DATA_WIDTH_p" Value="16"/> <Property Name="COEFF_WIDTH_p" Value="16"/> <Property Name="NUM_TAPS_p" Value="64"/> </Instance> <Connection Name="in_to_asm_rx_path_from_adc" External="consumer"> <Port Instance="dc_offset_filter" Name="in"/> </Connection> <Connection> <Port Instance="dc_offset_filter" Name="out"/> <Port Instance="iq_imbalance_fixer" Name="in"/> </Connection> <Connection> <Port Instance="iq_imbalance_fixer" Name="out"/> <Port Instance="complex_mixer" Name="in"/> </Connection> <Connection> <Port Instance="complex_mixer" Name="out"/> <Port Instance="cic_dec" Name="in"/> </Connection> <Connection> <Port Instance="cic_dec" Name="out"/> <Port Instance="rp_cordic" Name="in"/> </Connection> <Connection> <Port Instance="rp_cordic" Name="out"/> <Port Instance="rx_fir_real" Name="in"/> </Connection> <Connection Name="out_from_asm_rx_path" External="producer"> <Port Instance="rx_fir_real" Name="out"/> </Connection> </HdlAssembly>- Your assembly Makefile
This file is protected by Copyright. Please refer to the COPYRIGHT file
distributed with this source distribution.
This file is part of OpenCPI http://www.opencpi.org
OpenCPI is free software: you can redistribute it and/or modify it under the
terms of the GNU Lesser General Public License as published by the Free
Software Foundation, either version 3 of the License, or (at your option) any
later version.
OpenCPI is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
details.
You should have received a copy of the GNU Lesser General Public License along
with this program. If not, see http://www.gnu.org/licenses/.
$(if $(realpath $(OCPI_CDK_DIR)),,$(error The OCPI_CDK_DIR environment variable is not set correctly.))
Containers=
cnt_1rx_1tx_thruasm_asdr
export VivadoExtraOptions_route:= -directive NoTimingRelaxation
DefaultContainers=
ExcludePlatforms=isim modelsim xsim
Libraries+=misc_prims util_prims dsp_prims comms_prims
include $(OCPI_CDK_DIR)/include/hdl/hdl-assembly.mk
- Your assembly container .xml
cnt_1rx_1tx_thruasm_asdr.xml
<!-- filename: cnt_1rx_1tx_thruasm_asdr.xml --> <!-- filename description: cnt (this is a container) --> <!-- 1rx (number of RX channels used) --> <!-- 1tx (number of TX channels used) --> <!-- thruasm (container architecture description) --> <!-- asdr (frontend and/or slot descriptions, if applicable) --> <!-- (other details, if applicable) --> <!-- asdr (platform description, if applicable) --> <!-- .xml --> <!-- CPU FPGA --> <!-- ______ _________________________________________ --> <!-- + + + + --> <!-- | | i | container ___ | --> <!-- | | n | + + | --> <!-- | |*t*|*********************************|dev| | --> <!-- | | e | (3) * +___+ | --> <!-- | | r | * | --> <!-- | | c | ______________ * | --> <!-- | | o | + assembly + *(1) | --> <!-- | | n | | | * | --> <!-- | | n | (2) | | * | --> <!-- | |*e*|*********| |**** | --> <!-- | | c | | | | --> <!-- | | t | | | | --> <!-- +______+ +_________+_____________+_________________+ --> <!-- --> <HdlContainer Config="cfg_1rx_1tx_m2" Platform="asdr"> <!-- (1) external-to-FPGA device (worker) to FPGA assembly connections --> <!--Connection External="<assembly_port_name>" Port="<device_port_name>" Device="<device_name>" Card="<card_name>" (required if card is used) Slot="<slot_name>" (required if more than one platform slot of the card slot type exists) --> <!-- e.g. <Connection External="in_to_asm_rx_path_from_adc" Port="out" Device="lime_adc"/> --> <!-- e.g. <Connection External="out_from_asm_tx_path_to_dac" Port="in" Device="lime_dac"/> --> <Connection External="in_to_asm_rx_path_from_adc" Port="out" Device="ad9361_adc0"/> <Connection External="out_from_asm_tx_path_to_dac" Port="in" Device="ad9361_dac0" /> <!-- (2) FPGA assembly to CPU interconnect connections --> <!--Connection External="<assembly_port_name>" Interconnect="<interconnect_name, probably zynq or pcie>"/--> <!-- e.g. <Connection External="out_from_asm_rx_path" Interconnect="zynq"/> --> <!-- e.g. <Connection External="in_to_asm_tx_path" Interconnect="zynq"/> --> <Connection External="out_from_asm_rx_path" Interconnect="zynq"/> <Connection External="in_to_asm_tx_path" Interconnect="zynq"/> <!-- (3) external-to-FPGA device (worker) to CPU interconnect connections (bypassing the assembly)--> <!--Connection Device="<device_name>" Port="<device_port_name>" Card="<card_name>" (required if card is used) Slot="<slot_name>" (required if more than one platform slot of the card slot type exists) Interconnect="<interconnect_name, probably zynq or pcie>"/--> <!-- e.g. <Connection Device="lime_adc" Port="out" Interconnect="pcie"/> --> <!-- e.g. <Connection Device="lime_dac" Port="in" Interconnect="pcie"/> --> </HdlContainer>From: "Brandon Luquette" bluquette@geontech.onmicrosoft.com
To: "Devin Ridge" devinr@vt.edu, "discuss" discuss@lists.opencpi.org
Sent: Tuesday, April 30, 2019 11:34:05 AM
Subject: Re: hdl platform port mapping
Devin,
Mapping a signal from the ad9361_data_sub device worker to a pin name in the XDC is certainly a valid action. To help further debug the error, can you send us the following:
- The line in your .xdc containing PAD_PL_CAT_P1_D_6
- Your assembly .xml
- Your assembly Makefile
- Your assembly container .xml
Thanks,
Brandon
From: discuss discuss-bounces@lists.opencpi.org on behalf of Devin Ridge devinr@vt.edu
Sent: Tuesday, April 30, 2019 10:27 AM
To: discuss
Subject: [Discuss OpenCPI] hdl platform port mapping
We encountered the following error regarding external signal PAD_PL_CAT_P1_D_6
We are attempting to map the signal from the AD9361_data_sub platform worker to the correct pin name in the platform XDC file.
Included below is a subset of the device worker instance. Is there an issue with how we are mapping the ports in the platform spec?
Is it necessary to specify these signals in the hdl container and/or assembly also?
Our alternative approach is to modify the XDC file to match the pin names to the AD9361 worker port names to alleviate the need for port mapping, however we need to understand how to map the ports.
=======End generated platform configuration assembly=======
For file gen/fsk_modem_asdr_cfg_1rx_1tx_m2_cnt_1rx_1tx_thruasm_asdr.xml: in HdlContainerAssembly for fsk_modem_asdr_cfg_1rx_1tx_m2_cnt_1rx_1tx_thruasm_asdr: External signal "PAD_PL_CAT_P1_D_6" specified for signal "ad9361_data_sub_P1_D_11_6(0)" of instance "pfconfig" of worker "cfg_1rx_1tx_m2" is not an external signal of the assembly
make[3]: Entering directory /home/hume-users/devinr/ocpi_projects/bsp_asdr/hdl/assemblies/fsk_modem/container-fsk_modem_asdr_cfg_1rx_1tx_m2_cnt_1rx_1tx_thruasm_asdr' /opt/opencpi/cdk/include/hdl/hdl-container.mk:112: *** Failed to process initial parameters for this worker: 1. Stop. make[3]: Leaving directory /home/hume-users/devinr/ocpi_projects/bsp_asdr/hdl/assemblies/fsk_modem/container-fsk_modem_asdr_cfg_1rx_1tx_m2_cnt_1rx_1tx_thruasm_asdr'
make[2]: *** [container-fsk_modem_asdr_cfg_1rx_1tx_m2_cnt_1rx_1tx_thruasm_asdr/target-zynq/fsk_modem_asdr_cfg_1rx_1tx_m2_cnt_1rx_1tx_thruasm_asdr.bitz] Error 2
make[2]: Leaving directory /home/hume-users/devinr/ocpi_projects/bsp_asdr/hdl/assemblies/fsk_modem' make[1]: *** [fsk_modem] Error 2 make[1]: Leaving directory /home/hume-users/devinr/ocpi_projects/bsp_asdr/hdl/assemblies'
make: *** [hdlassemblies] Error 2
In the platform spec the device worker instance port mapping is specified as:
<device worker='ad9361_data_sub'>
<Signal name='P1_D_5_0(0)' platform='PAD_PL_CAT_P1_D_0' />
<Signal name='P1_D_5_0(1)' platform='PAD_PL_CAT_P1_D_1' />
<Signal name='P1_D_5_0(2)' platform='PAD_PL_CAT_P1_D_2' />
<Signal name='P1_D_5_0(3)' platform='PAD_PL_CAT_P1_D_3' />
<Signal name='P1_D_5_0(4)' platform='PAD_PL_CAT_P1_D_4' />
<Signal name='P1_D_5_0(5)' platform='PAD_PL_CAT_P1_D_5' />
<Signal name='P1_D_11_6(0)' platform='PAD_PL_CAT_P1_D_6' />
<Signal name='P1_D_11_6(1)' platform='PAD_PL_CAT_P1_D_7' />
<Signal name='P1_D_11_6(2)' platform='PAD_PL_CAT_P1_D_8' />
<Signal name='P1_D_11_6(3)' platform='PAD_PL_CAT_P1_D_9' />
<Signal name='P1_D_11_6(4)' platform='PAD_PL_CAT_P1_D_10' />
<Signal name='P1_D_11_6(5)' platform='PAD_PL_CAT_P1_D_11' />
</device>
Devin