I familiarized myself with OpenCPI device -> platform mapping with my Pluto port and I am now getting into a more complex design which has multiple AD9361 devices connected to the same FPGA using LVDS. I tried mapping P0_D_5_0 to a platform signal that was 6 bits wide, and I keep failing when I go to make my assembly. There are data_sub_ signals defined which look like they should be the data signals, but they don't have the correct P0_D_5_0 designation. Where in the OpenCPI tool code base can I look, or what debug can I look at to figure out why the mapping is being ignored or not being applied correctly? Mapping to single pins was fine and understandable when it was the CMOS interface and there were 2 different ports which needed to be mapped over, but this just seems broken now. Any insight would be appreciated on helping with the mappings. Also note - I am not opposed to adding an index positions for slicing vectors if that makes sense. Something like: <signal name="P0_D_5_0" platform="tx_data" inidx="0" outidx="0"> <signal name="P0_D_11_6" platform="tx_data" inidx="0" outidx="6> Resulting in ... P0_D_5_0 => tx_data(5 downto 0), P0_D_11_6 => tx_data(11 downto 6) Does something like this exist or would be acceptable? I don't think I am doing anything incorrectly. Thanks, Brian